A conventional method of manufacturing a semiconductor device where a wiring layer is formed is described with reference to FIGS. 1A-1H. In FIG. 1A, a dielectric film 12 such as silicon dioxide (SiO.sub.2) is deposited on a silicon substrate 11 (i.e., a wafer) containing an underlying integrated circuit device (not shown). The surface of the deposited dielectric film may have dents 13 due to, for example, previous processing and/or underlying structures as shown in FIG. 1A.
A photosensitive resin layer is then formed on dielectric film 12. Thereafter, the photoresist is aligned and exposed with a desired wiring pattern. The photoresist undergoes a development process to form a photoresist pattern 14 as shown in FIG. 1B. Dielectric film 12 is selectively etched using a reactive ion etching (RIE) method with the photoresist pattern 14 serving as a mask. The resulting structure is shown in FIG. 1C. Following the etching, the photoresist pattern 14 is removed, thereby leaving the structure shown in FIG. 1D.
Next, a titanium nitride (TiN) film 15 is deposited on dielectric film 12 producing the structure shown in FIG. 1E. Using a blanket chemical vapor deposition (CVD) method, a tungsten film 16 is then deposited on TiN film 15 producing the structure shown in FIG. 1F. TiN film 15 acts as a seed layer and an adhesion layer for the deposition of the tungsten film.
Thereafter, the tungsten film 16 and the TiN film 15 are polished. Since the polishing rates of TiN film 15 and tungsten film 16 are generally much greater than the polishing rate of dielectric film 12, it would be expected that dielectric film 12 would function as a polish stop. However, in practice if dielectric film 12 is exposed, tungsten film 16 becomes overpolished, thereby causing dishing. Further, the load or down force of the polishing pad tends to become concentrated on the surface of dielectric film 12 so as to result in a surface topography as shown in FIG. 1G. As a result, the wiring layer becomes thinner, thereby adversely affecting tie performance and reliability of the semiconductor device. An increase in wiring resistance results (sheet resistance) when thinning occurs. For example, when the aforementioned conventional method was applied, wiring resistance (i.e., sheet resistance) varied from 0.8 ohm/sq to 2.3 ohm/sq, although a desired wiring resistance ranged from 0.7 ohm/sq to 0.9 ohm/sq. Moreover, the exposure of conductive layers under the TiN film 15 can result in undesirable electrical short circuits.
If the layer of material is underpolished, then the layer of material will likely be insufficiently planarized or remain too thick. Consequently, subsequent electrical contact processing may not completely remove portions of the layer of material resulting in the formation of undesirable electrical open circuits.
Even assuming that there is sufficient selectivity between the polishing rates of tungsten and dielectric film 12 (e.g., SiO.sub.2), other problems can result. As shown in FIG. 1H, dents 13 are located on the surface of dielectric film 12. If polishing stops on the surface of dielectric film 12, the TiN and/or the tungsten remains not only in grooves that become wiring, but also in dents 13. When metal (e.g., tungsten and TiN) is present in the dents 13, short circuits can result. For example, in devices manufactured according to the above method, the short yield was 77% for a 0.3 .mu.m line and 0.3 .mu.m space pattern.
Problems with the conventional method are not only limited to the polishing process. The blanket CVD method for depositing tungsten film 16 on TiN film 15 also has several disadvantages. For example, a tungsten film tends to grow on the wall of the CVD chamber as tungsten film 16 is deposited on the wafer. Growth of the tungsten film on the wall of a CVD chamber can prevent tungsten from evenly growing from the bottom of the trench. In addition, the rate of deposition using a blanket deposition method is generally slow and it is difficult to fill narrow trenches or through holes (e.g., contacts, vias) due to the occurrence of voids and shims. Further, the tungsten film deposited on the wall of the chamber can peel off causing the wafer to be contaminated.